| 1. Identity statement | |
| Reference Type | Conference Paper (Conference Proceedings) |
| Site | sibgrapi.sid.inpe.br |
| Holder Code | ibi 8JMKD3MGPEW34M/46T9EHH |
| Identifier | 83LX3pFwXQZW44Lb/d4S7S |
| Repository | dpi.inpe.br/ambro/1998/05.06.14.50 |
| Last Update | 1998:05.25.03.00.00 (UTC) administrator |
| Metadata Repository | sid.inpe.br/banon/2001/03.30.15.55.59 |
| Metadata Last Update | 2022:06.17.22.27.52 (UTC) administrator |
| ISBN | 85-244-0103-6 |
| Citation Key | Barros:1996:MePrIm |
| Title | Uma metodologia de projeto e implementação de operadores para processamento digital de imagens em tempo real usando field programmable gate arrays  |
| Format | Impresso, On-line. |
| Year | 1996 |
| Access Date | 2024, Apr. 29 |
| Number of Files | 1 |
| Size | 92 KiB |
| 2. Context | |
| Author | Barros, Marcelo |
| Editor | Velho, Luiz Albuquerque, Arnaldo de Lotufo, Roberto A. |
| Conference Name | Simpósio Brasileiro de Computação Gráfica e Processamento de Imagens, 9 (SIBGRAPI) |
| Conference Location | Caxambu, MG, Brazil |
| Date | 29 Oct.-1 Nov. 1996 |
| Publisher | Sociedade Brasileira de Computação |
| Publisher City | Porto Alegre |
| Pages | 297-304 |
| Book Title | Anais |
| Tertiary Type | Artigo |
| Organization | SBC - Sociedade Brasileira de Computação; UFMG - Universidade Federal de Minas Gerais |
| History (UTC) | 2008-07-17 14:17:56 :: administrator -> banon :: 2010-08-28 20:04:50 :: banon -> administrator :: 2013-04-05 16:31:24 :: administrator -> banon :: 1996 2013-04-05 16:35:12 :: banon -> administrator :: 1996 2022-06-17 22:27:52 :: administrator -> banon :: 1996 |
| 3. Content and structure | |
| Is the master or a copy? | is the master |
| Content Stage | completed |
| Transferable | 1 |
| Abstract | This paper presents an efficient approach to implement low-level image processing algorithms using a reconfigurable hardware technology. The Xilinx Field Programmable Gate Array (FPGA) circuits are used. We describe a synthesis method to generate separable 2D filter architectures on Xilinx FPGAs is evaluate. Time and area constraints are specially considered. An architecture is proposed which allows real time operation of large kernel filters. We present the implementation of a set of basic operators used to build current linear and non-linear (morphological) 2D filters. |
| Type | Processamento de Imagens |
| Arrangement 1 | urlib.net > SDLA > Fonds > Full Index > Uma metodologia de... |
| Arrangement 2 | urlib.net > SDLA > Fonds > SIBGRAPI 1996 > Sumário > Uma metodologia de... |
| Arrangement 3 | urlib.net > SDLA > Fonds > SIBGRAPI 1996 > Sumário > Índice > Uma metodologia de... |
| doc Directory Content | access |
| source Directory Content | there are no files |
| agreement Directory Content | there are no files |
| 4. Conditions of access and use | |
| data URL | http://urlib.net/ibi/83LX3pFwXQZW44Lb/d4S7S |
| zipped data URL | http://urlib.net/zip/83LX3pFwXQZW44Lb/d4S7S |
| Language | pt |
| Target File | a68.pdf |
| User Group | administrator banon |
| Visibility | shown |
| 5. Allied materials | |
| Mirror Repository | sid.inpe.br/sibgrapi@80/2007/08.02.16.22 |
| Next Higher Units | 8JMKD3MGPEW34M/4742MCS 8JMKD3MGPBW34M/3DRR7SB 8JMKD3MGPBW34M/3DRRJT5 |
| Citing Item List | sid.inpe.br/sibgrapi/2013/04.05.14.57 1 sid.inpe.br/banon/2001/03.30.15.38.24 1 |
| Host Collection | sid.inpe.br/banon/2001/03.30.15.38 |
| 6. Notes | |
| Empty Fields | affiliation archivingpolicy archivist area callnumber contenttype copyholder copyright creatorhistory descriptionlevel dissemination documentstage doi e-mailaddress edition electronicmailaddress group issn keywords label lineage mark nextedition notes numberofvolumes orcid parameterlist parentrepositories previousedition previouslowerunit progress project readergroup readpermission resumeid rightsholder schedulinginformation secondarydate secondarykey secondarymark secondarytype serieseditor session shorttitle sponsor subject tertiarymark url versiontype volume |
| 7. Description control | |
| e-Mail (login) | banon |
| update | |